Essentials of Professional VLSI Digital Design | Edureka


Become an advanced user of Verilog/System-Verilog Hardware Description Language: Learn the key language syntax and practical usage scenarios, enabling students to create a functioning digital design, simulate the design and understand gate-level implementation of the design by synthesis using TSMC018 standard cell library. Assimilate the must-know concepts and good practices of digital design through 28 hours of lectures and 30 hours of well-structured labs/mini-projects in a professional VLSI development environment built around LINUX, Perl and ModelSim.

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